The proliferation of low-power applications has driven the need to reduce the power consumption of the circuits used in low-power devices. For example, battery life extension for portable devices, such as cell phones and computers, is of increasing concern as the density and complexity of the circuits used in these devices increases. One solution focuses on lowering the power supply and operating voltages, which requires that the threshold voltages of the transistors used in the circuits be reduced to reach performance guidelines. However, reducing the transistor threshold voltages deleteriously increases the leakage current of the transistors due to the exponential relationship between threshold voltage and leakage current. This becomes more problematic especially as power supply and operating voltages and the corresponding threshold voltages are ever reduced.
Power consumption in devices that are intermittently operated is typically reduced by configuring the circuits of such devices to operate in an idle or standby state after a period of inactivity. Such circuits consume power even in the idle state, however, so it is desirable to reduce the power consumption of the circuits in the idle state. Methods for reducing power consumption in the idle state by defining an input vector have previously been proposed, but such power consumption reduction methods do not take into account the circuit structure of the digital circuit.
In particular, previous methods propose subjecting a circuit to random input state vector generation to obtain an input state vector that, when applied to a digital circuit, results in reduced power consumption when the digital circuit is in an idle state. An example of such a method is disclosed by Halter et al. in A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits, PROC. IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE, 475–478 (1997). However, the approach of Halter et al. does not take the circuit structure into account when determining the input state vector. In addition, at least some randomly-generated input state vectors will not actually reduce the power consumption of the digital circuit in the idle state.
Other methods propose applying a genetic algorithm and linear normalization to determine an input state vector. An example of such a method is disclosed by Chen et al. in Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks, PROC. IEEE & ACM INT. SYMPOSIUM ON LOW POWER ELECTRONICS & DESIGN, 239–244(August 1998). However, the final input state vector obtained by the genetic algorithm depends largely on the initial vector set chosen. If the initial vector set is non-optimum, the resulting input state vector may not actually be the input state vector that best reduces the power consumption in the digital circuit in the idle state.
Still other methods reduce power consumption of a digital circuit in an idle state by using multiplexers to apply the input state vector to the inputs of the digital circuit. An example of this is disclosed by U.S. Pat. No. 6,081,135 of Goodnow et al., entitled Device and Method to Reduce Power Consumption in Integrated Semiconductor Devices. However, the addition of multiplexers to apply the input state vector increases the power consumption of the digital circuit when the circuit is in its active state. The additional multiplexers also increase the power consumption of the digital circuit in the idle state.
Additionally, when determining an input state vector, it is possible that different approaches for determining an input state vector will generate conflicting state for one or more of the input states of the input state vector.
Therefore, there is a need for a method and apparatus for defining an input state vector that achieves low power consumption when applied to the circuit inputs of a digital circuit in an idle state. Additionally, there is need for a method and apparatus for defining such an input state vector that does not require changes in design methodologies and standard design cell libraries used to design the digital circuit.